1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to an SGT (Surrounding Gate Transistor) which is a vertical MOS transistor comprising a pillar-shaped semiconductor layer having a sidewall serving as a channel region, and a gate electrode formed to surround the channel region.
2 . Description of the Related Art
With a view to achieving higher integration and higher performance of a semiconductor device, an SGT (Surrounding Gate Transistor) has been proposed which is a vertical transistor comprising a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see, for example, the following Patent Document 1: JP 2 -188966A). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupancy area can be significantly reduced as compared with a conventional planar transistor.
FIG. 50(a) shows a top plan view of a CMOS inverter fabricated using the SGT disclosed in the Patent Document 1, and FIG. 50(b) is a sectional view taken along the cutting-plane line A-A′ in the top plan view of FIG. 50(a).
Referring to FIGS. 50(a) and 50(b), an N-well 2502 and a P-well 2503 are formed in an upper region of a Si substrate 2501. A pillar-shaped silicon layer 2505 constituting a PMOS (PMOS pillar-shaped silicon layer 2505) and a pillar-shaped silicon layer 2506 constituting an NMOS (NMOS pillar-shaped silicon layer 2506) are formed on a surface of the Si substrate, specifically, on respective ones of the N-well region and the P-well region, and a gate 2508 is formed to surround the pillar-shaped silicon layers. A P+ drain diffusion layer 2510 formed underneath the PMOS pillar-shaped silicon layer, and an N+ drain diffusion layer 2512 formed underneath the NMOS pillar-shaped silicon layer, are connected to an output terminal Vout. A source diffusion layer 2509 formed on a top of the PMOS pillar-shaped silicon layer is connected to a power supply potential Vcc, and a source diffusion layer 2511 formed on a top of the NMOS pillar-shaped silicon layer is connected to a ground potential Vss. The common gate 2508 for the PMOS and the NMOS is connected to an input terminal Vin. In this manner, the CMOS inverter is formed.
Patent Document 1: JP 2 -188966A
As a prerequisite to applying an SGT to actual electronic products such as CPU, there is the following problem. In electronic products such as CPU, a logic circuit section requiring a high-speed operation is fabricated using a transistor having a minimum gate size L, whereas an I/O section for interfacing data communication with the outside is fabricated using a transistor having a longer gate length as compared with the transistor for the logic circuit section, because it is generally operated at an operating voltage greater than that for the logic circuit section. For example, given that an operating voltage for the logic circuit section is 1.0 V, the I/O section is operated at an operating voltage of 1.8 V or 2.5 V. Therefore, the transistor for the I/O section has a gate length about two or three times greater than that of the transistor for the logic circuit section.
Further, in a part of analog circuit sections and logic circuit sections for use in various other electronic products, a transistor having a longer gate length as compared with the transistor for a typical logic circuit section is also used.
As above, in actual electronic products, it is essential to concurrently form a plurality of transistors having various different gate lengths, on a chip. However, due to a basic structure of an elemental or unit SGT, it is difficult to form an SGT having a gate length greater than a gate length Ls of the unit SGT.